1. Field of the Invention
The present invention relates generally to electrically programmable and erasable memory, and more particularly, to injecting hot carriers in non-volatile memories.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a non-volatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Nitride read-only memory devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of an nitride read-only memory flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious as the technology continues to scale down.
A typical flash memory cell structure positions a tunnel oxide layer between a conducting polysilicon tunnel oxide layer and a crystalline silicon semiconductor substrate. The substrate refers to a source region and a drain region separated by an underlying channel region. A flash memory read can be executed by drain sensing or source sensing. For source side sensing, one or more source lines are coupled to source regions of memory cells for reading current from a particular memory cell in a memory array.
A traditional floating gate device stores one bit of charge in a conductive floating gate. The advent of nitride read-only memory device comprises multiple cells where each nitride read-only memory cell is capable of storing two bits of charges in an Oxide-Nitride-Oxide (ONO) dielectric. In a typical structure of an nitride read-only memory cell, a nitride layer is used as a trapping material positioned between a top oxide layer and a bottom oxide layer. The ONO layer structure effectively replaces the gate dielectric in floating gate devices.
The charge in the ONO dielectric with a nitrite layer may be either trapped on the left side or the right side of an nitride read-only memory cell.
A frequently used technique to program nitride read-only memory cells in an nitride read-only memory array is the hot electron injection method. During an erase operation, a common technique used to erase memory cells is called band-to-band tunneling hot hole injection where the erase ability is highly dependent on the lateral electric field. The side potential opposite that being erased of an nitride read-only memory cell is likely to have a lateral electric field effect on the eraseability. Evaluating the endurance and retention of an nitride read-only memory array, the lack of uniformity in eraseability causes a margin loss due to cycling and baking. The other side of nitride read-only memory cells are left floating (or connected to ground) and may be coupled to an uncertain voltage level (e.g. 1 volt or 4 volts), which causes variation of the erase threshold of array cells. This in turn causes Vt distribution after an erase operation to be wider.
An nitride read-only memory type of device typically undergoes a series of program and erase cycles which causes electrons to migrate closer to the middle of a channel region. In a subsequent erase operation using a technique such as BTBTHH, it would be difficult to move holes toward the middle of the channel region which makes the residual electrons located near the channel region hard to erase. The hard-to-erase scenario typically occurs in a multi-bit cell like nitride read-only memory with localized hot electron and hot hole injection program and erase schemes.
A nitride-based charge-trapping flash memory device has been gaining wider acceptance as a candidate for a next generation of flash memories due to its high compatibility with simpler Si CMOS fabrication processes, which avoids or eliminates the occurrence of erratic bits, drain turn-on and coupling issues. The ability to shrink the dimensions of the memory device is also desirable for high-density stand alone or embedded memories application. In comparison with traditional SONOS memory with a thin tunneling oxide, a thicker bottom oxide is selected to achieve better data retention, but the thicker bottom oxide is not desirable for a NAND-type nitride trapped memory application. For NAND applications, programming and erasing operations are typically performed using the Fowler-Nordheim (FN) tunneling technique. A drawback of the FN tunneling technique is the extremely low FN tunneling rate of electrons and holes.
Accordingly, it is desirable to have a hot carrier injection method for a charge trapping memory with a NAND or related structure that injects a faster rate of electrons or holes.